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I write HW models in C++ and then translate to verilog when working, the last stage is usually to replace the {} parentheses with "begin" "end" blocks, this is left to the end as the {} make parentheses matching possible when editing the code.
unfortunately {} are also used in verilog for concatenating vectors, so the replacement is a tedious process.

It would be nice to be able to identify keyword matching, i.e. behave the same as parenthes matching but with keywords.

for example begin - end
case - endcase
module - endmodule

then I could perform the {} replacement at the start and still keep the ability to match block start - end

since the keywords are inevitably defined in the .syn file a nice feature would be to be able to identify keyword pairings in this manner, e.g. allocate keywords a group number, and for each group have a set of start and end keywords, this should then suit many languages.


this would make the editor much more useful for editing HW descriptions languages.